Sun SPARC

Sun UltraSparc II.

SPARC (from Scalable Processor ARChitecture) is a big-endian RISC architecture. That is, an architecture with a reduced instruction set.

Originally designed by Sun Microsystems in 1985, it is based on the University of California at Berkeley RISC I and II designs that were defined between 1980 and 1982.

The company Sun Microsystems designed this architecture and licensed it to other manufacturers such as Texas Instruments, Cypress Semiconductor, Fujitsu, LSI Logic among others.

SPARC is the first open RISC architecture and as such the design specifications are published so that other microprocessor manufacturers can develop their own design.

One of the innovative ideas of this architecture is the registers window that allows to easily make high performance compilers and a significant memory reduction in load/store instructions relative to other RISC architectures. The advantages are seen above all in large programs.

The SPARC CPU is composed of an Integer Unit (IU), which processes basic execution, and a Floating Point Unit (FPU), which performs real number calculations and operations. The UI and FPU may or may not be built on the same chip.

Although not a formal part of the architecture, computers based on Sun Microsystems SPARC systems have a memory management unit (MMU) and a large virtual address cache (for instructions and data) that are arranged peripherally on a data bus and 32-bit addresses.

Main features

• Its distinctive feature is to use log windows.
• 32 whole 32-bit records.
• 16 64-bit floating comma logs (for double-precision) that can be used as 32 32-bit logs (for simple accuracy).
• Direction modes:
  • Immediately, 13-bit counts.
  • Straight, 13-bit offset.
  • Indirect, (record + offset of 13 bits or record + record).
• Use delayed instructions (salts, load and store).
• Memory management:
  • Virtual space of 4 Gigabytes.
  • Memory management unit (MMU) that works with configurable size pages.

Instruction Categories

The SPARC architecture has about 50 integer instructions, a few more than the previous RISC design, but less than half the number of integer instructions in Motorola's 6800.

SPARC instructions can be classified into five categories:

• LOAD and STORE (the only way to access memory). These instructions use two logs or a record and a constant to calculate the memory address to address.

• Arithmetic/Legical/Shift Instructions. Run arithmetic operations, logics and bit displacement. These instructions calculate the result if it is a 2 operating function and save the result in a registry.

• Coprocessor operations. The IU extracts the floating comma operations from the data bus instructions and places them in the tail for the UPDF. The UPDF executes the floating comma calculations with a fixed number in arithmetic unit of floating comma (the number is dependent on the application). The floating comma operations are performed concurrently with IU instructions and other floating comma operations when necessary. The SPARC architecture also specifies an interface for the connection of an additional coprocessor.

• Transfer Control Instructions. These include jumps, calls, rags and branches. Transfer control is usually delayed until after the execution of the next instruction, so the pipeline is not emptied because time control occurs. Thus, compilers can be optimized by retarded branches.

• Records control instructions Read/Write. These instructions are included to read and record the contents of several control records. Generally the source or destination is implied in the instruction.

Log windows

A unique feature of the SPARC design is the window with overlapping registers. The processor has much more than 32 integer registers, but it presents 32 at any given time. An analogy can be created by comparing the register window to a rotating wheel. Some part of the wheel is always in contact with the ground; so turning it takes different portions of the wheel (the effect is similar for the record window overlap). The result of a register is changed to an operand for the next operation, obviating the need for an extra Load and Store statement.

It was agreed for the specification of the architecture, to be able to have 32 "visible" Divide into groups of 8.

• From r0 to r7, GLOBAL records.
• From r7 to r15, SALIDA records.
• From r15 to r23, LOCAL records.
• From r24 to r31, ENTRADA records.

Global records are "viewed" by all windows, the locales are only accessible by the current window, and the output registers overlap the input registers of the next window (the output registers for one window should be set as input records for the next, and should be in the same registry).

The window pointer keeps track of which window is currently active. There are instructions for "opening" and "close" windows, for example for a "call" instruction, the register window rotates anti-clockwise; for return from a "call" instruction, it rotates clockwise.

An interrupt uses a fresh window, that is, it opens a new window. The number of windows is an implementation parameter, usually 7 or 8.

The more elaborate alternative to slowly circling the log window is to place the logs at compile time. For languages like C, Pascal, etc., this strategy is difficult and time consuming. Therefore, the compiler is crucial to improve the productivity of the program.

"Recent research suggests that window registers, found on SPARC systems but not on other commercial RISC machines, are able to provide excellent performance for development languages such as Lisp and Smalltalk." (R. Blau, P. Foley, etc. 1984).

Traps and Exceptions

The SPARC design supports a full set of traps or interrupts. They are managed by a table that supports 128 hardware interrupts and 128 software traps. Although floating point instructions can be executed concurrently with integer instructions, floating point traps must be exact because the FPU provides (from the table) the addresses of the instructions that fail.

Memory protection

Some SPARC instructions are privileged and can only be executed while the processor is in supervisor mode. These instructions executed in protected mode ensure that user programs are not accidentally altered by the state of the machine with respect to its peripherals and vice versa. The SPARC design also provides memory protection, which is essential for multitasking operations.

The SPARC has many similarities to the Berkeley design, the RISC II. Similar to RISC II, it uses a register window to reduce the number of Load and Store instructions.

SPARC according to Sun Microsystems

Until recently, the RISC architectures had a poor performance regarding floating comma calculations. For example, IBM 801 was implementing software-floating coma operations. Berkeley, RISC I and RISC II projects exceeded a VAX 11/780 in whole calculations but NOT in arithmetic floating coma. This is also true for the Stanford processor, the MIPS. SPARC systems, however, are designed for optimal performance in floating comma calculations and support simple, double and extended precision in the operating and operations as specified by the ANSI/IEEE standard 754 of the floating comma standard.

The high performance in floating comma calculations results from the concurrence of the IU and the UPDF. The IU (Integer Unit) makes the "load" and "store" while the FPU (Floating Point Unit) executes operations and calculations.

SPARC systems achieve high speeds as a result of refinement in chip manufacturing techniques.

The SPARC system delivers very high levels of performance. The flexibility of architecture makes future systems capable of obtaining many better times than that of initial implementation. In addition, open architecture makes this possible to absorb technological advances almost as soon as these occur.

^{[chuckles]required]}

Implementations

SPARC

• First generation released in 1987.
• Watch frequency from 16 to 50 MHz.
• Scaling design.

SUPER SPARC

• Second generation released in 1992.
• Watch frequency from 33 to 50 MHz.
• Superscale design

ULTRA SPARC II

• Launched in mid-1996.
• Super climbing architecture of 4 stages and 64 bits.
• Five units of floating comma.
• Speeds between 250 and 300 MHz.

Advanced Product Line (APL)

• Launched in mid-2004.
• Trade Agreement between Sun Microsystems and Fujitsu
• Super-scale architecture compatible with 64-bit SPARC V9 design.
• Speeds between 1.35 and 2.7 GHz.

Used by Sun Microsystems, Cray Research, Fujitsu / ICL and others.

SPARC Microprocessors Specifications

This table contains the specifications of certain SPARC processors: frequency (megahertz), architecture version, year of release, number of threads (threads per core multiplied by the number of cores), manufacturing process (nanometers), number transistors (millions), die size (mm²), number of input/output pins, power dissipated (watts), voltage and sizes of data, instruction, L2 and L3 caches (kibibytes).

Notes: