Motorola 68020

XC68020, a prototype of 68020.

Motorola 68020.

inferior view of an Motorola XC68020.

The Motorola 68020 is a 32-bit microprocessor from Motorola, released in 1984. It is the successor to the 68010, and was succeeded by the 68030.

Description

The 68020 (often called the '020, pronounced oh-two-oh or oh-twenty in English) has internal and external data buses and 32-bit addresses. A lower cost version, the 68EC020, has a 24-bit address bus only. They were manufactured in a range of speeds from 12 MHz to 33 MHz.

Improvements over the 68010

The 68020 added many improvements over the 68010 including a 32-bit arithmetic logic unit, 32-bit external data bus and address bus, and new instructions and address modes. The 68020 (and 68030) is based on a proper three-state pipeline architecture.

The addressing restrictions on word and longword data access present in its predecessors disappear in the 68020.

Multithreading Capabilities

Motorola's multithreading model was added in the 68020. This allowed up to eight processors per system to cooperate, these eight could be any number of CPU FPUs but only one MMU (Motorola 68841 or Motorola 68851). This had some limitation, as each CPU used had to be of the same model (not necessarily at the same clock frequency) and each FPU had to be of the same model (again, not necessarily at the same clock frequency) so multithreading a 68020/25 with a 68030/25 was not allowed (the 020, for example, couldn't be identified by the 030's internal MMU) but a 68020/25 with a 68882/33 was perfectly acceptable and quite common. However it was very rare to see more than one CPU or FPU in the same system. Most 68020-equipped Unix machines were simply the '020, the FPU (68881 or 68882) and the MMU (68841 or 68851).

Instruction Set

The new instructions included some minor enhancements and extensions to the supervisor state, several instructions for software management of a multithreaded system (which were removed on the 68060), some support for high-level programming languages that not used much (and also removed in future 680x0), older multiplication (32×32→64-bit) and division (quotient 64÷32→32-bit and 32-bit remainder) instructions, and field manipulations at the bit level.

Addressing Modes

The new Addressing Modes added scaled address indexing and another level of memory indirection to many of the existing modes, and added a lot of flexibility to various indexing modes and operations. Although not intended, the new modes made the 68020 very convenient for page printing. Most early 90's laser printers had a 68EC020 at their core.

The 68020 has a minimum instruction cache of 256 bytes directly mapped, arranged as 64 4-byte entries. Although small, it is a significant difference in the performance of many applications. The resulting decrease in bus traffic is particularly important in systems that used direct memory access (DMA) intensively.

Use

Macintosh LC pizza box

The 68020 was used in Apple Computer Macintosh II and Macintosh LC personal computers, Sun-3 series workstations, and the Hewlett Packard 8711 series of network analyzers. The Commodore Amiga 1200 personal computer and AmigaCD32 game console, both from Commodore, used the 68EC020 to reduce costs.

It is also the processor used in the TGV trains to decode the signaling information that is sent to the trains via the rails, and in its military version it is the CPU of the computers of the Eurofighter Typhoon fighter plane as well as in the launcher Ariane 5.

For more information on instructions and architecture, see Motorola 68000.