Intel 80486

The Intel 80486 (i486, 486) are a family of 32-bit microprocessors with x86 architecture designed and manufactured by Intel Corporation and also manufactured by license or reverse engineered by other companies such as IBM, Texas Instruments, AMD, Cyrix and Chips and Technologies with different or cloned designs.

The i486s are very similar to their predecessors, the Intel 80386s. The main differences are that the i486s have an optimized instruction set, a floating-point unit, and a unified cache built into the microprocessor's own IC, and a improved bus interface. These improvements make the i486 twice as fast as an i386 and i387 at the same clock rate. Some low-end i486s are slower than faster i386s anyway.

Typical clock speeds for i486s were:

• 16 MHz (not very frequent)
• 20 MHz (tampoco frequent)
• 25 MHz
• 33 MHz
• 40 MHz
• 50 MHz (typically a 25 MHz motherboard with clock duplication within the microprocessor)
• 66 MHz (33 MHz with clock duplication)
• 75 MHz (25 MHz with clock crew)
• 80 MHz (40 MHz AMD version with clock duplication)
• 100 MHz (33 MHz with clock crew)
• 120 MHz (40 MHz with clock crew, exclusive of AMD).

There was a 133 MHz 80486 made by AMD called Am5x86-P75 that had 16 KB L1 cache, 0.35 micron architecture (versus 0.6 micron in previous models), a 4x multiplier and FSB of 33 MT/s, of which different versions were also manufactured with different voltages and different encapsulations, 3.3 V and 3.45 V, enabling enormous overclocking capacity that allowed it to go up to 160 MHz, matching its performance with that of a Pentium-90. AMD later designed the 150 MHz Am5x86-P75+, 16 KB L1 cache, 3x multiplier, and 55 MT/s 3.45 V FSB, making it the most powerful 80486 processor ever made, with hardly any units ever being sold and a prized item. collector's item among fans.

The successor to the Intel 80486 microprocessor is the Intel Pentium.

Variants of the i486DX2

Intel 80486-SX / 33 MHz.

Architecture of 486DX2.

There are several variations on the basic design of the i486, including:

• Intel 80486-DX - the model version, with the features indicated above.
• Intel 80486-SX - an i486DX with the default-disabled floating point unit (later would be disabled even without default to cover the growing demand for SX models).
• Intel 80486-DX2 - an i486DX that internally works at twice the speed supplied by the external clock, to which the rest of the system devices work.
• Intel 80486-SX2 - an i486SX that works internally at double the clock speed.
• Intel 80486-SL - an i486DX with an energy saving unit.
• Intel 80486-SL-NM - an i486SX with an energy saving unit.
• Intel 80486DX4 - like an i486DX2 but triplicate internal speed.
• Intel 80487 or 80487-SX - an i486DX version designed to be used as i486SX floating comma unit. The i487 is installed on the coprocessor socket that is for the purpose on the base plates for i486SX. which was a complete 486DX that disabled the 486SX
• Intel 80486 OverDrive (486SX, 486SX2, 486DX2 or 486DX4) - variations of previous models designed as update processors, which have a different voltage. They were usually designed to be used on base plates that did not support the equivalent microprocessor directly.

Clock doubling and tripling

In order not to demand higher speeds from motherboards, Intel introduced doubling (and later tripling) clock frequency within the chip. While the motherboard and its communications with the microprocessor through its pins were carried out at the clock frequency, the internal operations of the microprocessor were carried out at double (or triple) speed. In this way, the code blocks loaded in the internal cache achieved a much higher performance, which dropped by half (or a third) when accessing RAM memory.

Intel designated microprocessors that used clock frequency doubling with the suffix "2". The frequency indicated in the microprocessor corresponded to the already doubled frequency. For example, the 66 MHz 80486 DX2 had a 33 MHz motherboard clock. The uninformed public accepted the suffix "2" as a sign of superiority, and it was widely believed that a 66 MHz 486 was twice as fast as 132 MHz. In seemingly contradictory fashion, most speed tests showed that a PC with a 40 MHz microprocessor (no speed doubling) was faster than a 50 MHz one (25 MHz speed doubling).

Surprisingly, Intel designated microprocessors that employed clock frequency tripling with the suffix "4" instead of "3", causing the uninformed public to overestimate the capabilities of these microprocessors. Thus, a 100 MHz 486 had a clock frequency of 33 MHz, and the frequency tripled to 99 MHz.

Application level instructions

Regarding the 386, three new instructions were added, two of them are oriented to the use of multiprocessor systems. In these it is usual to access shared resources and the regulation of these is done through traffic lights.

The third instruction added has the mission of facilitating access to the database of other processors such as those created to be used in IBM computers or equipment with Motorola microprocessors.

BSWAP reg32 Byte Swap Instruction

The BSWAP instruction is used to reverse the order of bytes in a 32-bit word. It converts a word stored with the object with the least weight in the lowest address into another that has the same, but with the least weight octet in the highest address. It provides better performance in ASCII and BCD arithmetic, since 4 octets are processed instead of just 1.

It is an instruction that only acts on 32-bit registers and executes in one clock cycle.

EAX 12345678HBSWAP EAX EAX 78563412H

Exchange and add instruction XADD r/m, reg

Use two operands of the same size 8, 16, or 32 bits. The second must be a record. The first can be a register or an operand in memory.

It runs in three or four clock cycles.

Example

XADDOPLOP2; OP2:=OP1; OP1:= OP1 + OP2IMOTEP ; OP3:=GATOIMOTEP,IMOTEP,IMOTEP,IMOTEPERROR LOG

Several processors could share the execution of the same instruction loop simplifying parallel processing.

With the new 486 instruction the encoding would be:

MOV EAX, 1LOCK XADD N, FAX

Compare and swap instruction CMPNCHG r m,reg

You need three operands of the same size 8, 16 or 32 bits. The second must be a record. The first can be a register or an operand in memory. The third must be implicit: the accumulator (AL, AX, EAX, depending on the size of the other operands). It runs in six or seven clock cycles if the comparison is true, or up to ten if it is false.

CMPXCHG DEST.ORGIA; IF DEST=ACUMTHEN DEST: ORGIA; THESE ACUM: =

The flags in the EFLAGS register indicate the result of the comparison. If o is true, ZF is set to 1; if not set to 0. You can perform multi-valued semaphores, and use the wait and signal instructions from multiple processes that want to share a resource simultaneously.

MOV EBX. IDENT_DAMBUCLEXOR EAX. EAXLOCK CMPCHG _ EBXJNZ BUCLEIf he's busy for another, wait.(Semaphore acquired: realization of the operation Protected)MOV _ 0The traffic light is released.

New system-level instructions

The 486 has four new instructions specific to it, which don't exist in the 386. Three of them are related to the 486's built-in internal cache for data and code. The fourth refers to the page table cache.

Loading and saving MOV TRn test records, reg32

Since there are three new registers related to the internal cache in the 486, they can also be accessed by the MOV function.

Invalidation of INVD cache content

With this, the contents of the internal cache are completely invalidated and a bus cycle is generated to indicate that the external caches should in turn invalidate their contents. The instruction is executed in four clock cycles.

Cache invalidation after WBINVD memory update

With this, the contents of the internal cache are completely invalidated and two bus cycles are generated, the first one tells the forced-write caches that they should update the main memory. To indicate to the second that in turn the external caches must invalidate their contents. The instruction is executed in 5 clock cycles.

Invalidation of a TLB (Translation Loackside Buffer) entry

Generates a virtual address from the given operand and invalidates the corresponding page table cache entry, the TLB. Invalidates the TLB entry that references the page that includes the address of the given memory operand. This instruction codes as INVLPG m and is executed in twelve cycles.

TLB test logs

Test registers are a formal part of the architecture 386 had for TLB archiving (TR6 AND TR7). The 486 adds another three more 32-bit registers to control the proper functioning of the internal cache of the processor.

The TR6 register is unchanged from the 386 register. TR7 adds a few more bits. These are:

• PCD: Bit PCD from the page table entry.
• PWT: PWD bit from the page table entry.
• LRU: When reading this field you get the value of the three bits used in the pseudo-LRU cache replacement algorithm.
• PL: Corresponds to the HT bit of the 386 TR7. In 486 you can write to one or zero.

Internal Cache Test Records

• TR3 stores data to transfer to cache memory.
• TR4 contains the test state.
• TR5 is the cache test control record.

They are all accessed by MOV instructions entered at the highest privilege level (zero).

TR4

• Valid: 4-bit validation for the 4-way sector.
• LRU.
• V: bit of validation of the concrete pathway that has been accessed between the 4 that belong to the same sector.
• Tag: force the value of the label to the assigned address in the field.

TR5

• CTL:
  • 00: Writing or reading of the intermediate memory of the cache.
  • 01: Cache writing.
  • 10: Reading of the cache.
  • 11: Cache invalidation. All positions are invalidated.
• ENT. In cache reading/writing select one of the four tracks in the selected sector. In R/W of the intermediate memory of the cache, select one of the four double words that make up the line.

Data Types

• Regular
• Enter
• Real
• BCD packaging
• 8, 16 and 32-bit chains
• 64 to 4 Gbit chains
• 8-bit ASCII features