Harvard architecture
The Harvard architecture is a computer architecture with physically separate signal and storage tracks for instructions and data. The term comes from the relay-based Harvard Mark I computer, which stored instructions on punched tapes (24-bit wide) and data in electromechanical switches. These early machines had data storage entirely contained within the central processing unit, and provided no access to instruction storage as data. The programs needed to be loaded by an operator; the processor could not boot by itself.
Most processors today implement such separate signal paths for performance reasons, but actually implement a modified Harvard architecture, so that they can support tasks such as loading a program from a disk drive as data for later execution.
Storage unit details
In the Harvard architecture, there is no need to make the two memories share characteristics. In particular, the word width, timing, implementation technology and memory address structure may differ. In some systems, instructions can be stored in read-only memory while, in general, data memory requires read-write memory. On some systems, there is much more instruction memory than data memory so instruction addresses are wider than data addresses.
Contrast with von Neumann architectures
Under pure von Neumann architecture, the CPU can either be reading an instruction or reading/writing data from/to memory but both processes cannot occur at the same time, since instructions and data use the same bus system. In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time, even without a cache. Consequently, a Harvard computer architecture may be faster for a complex circuit, because the instruction accesses data and does not compete for a single memory path.
In addition, the characteristics of the two memories are different, so the address of instruction space zero is not the same as the address of data space zero: Instruction memory address zero could identify a value of twenty-four bits, whereas data memory address zero zero could indicate an eight-bit value that is not part of that twenty-four-bit value.
Contrast with Modified Harvard Architecture
A modified Harvard architecture machine is very similar to a Harvard architecture machine, but relaxes the strict separation between instruction and data, while allowing the CPU to simultaneously access two (or more) bus memories. The most common modification includes separate instruction and data caches, backed by a common address space. While the CPU runs from the cache, it also acts like a pure Harvard machine. When backing memory is accessed, it acts like a pure von Neumann machine (where code can be moved around as data, which is a powerful technique). This modification has become widespread in modern processors, such as the ARM architecture and x86 processors. It is sometimes loosely called Harvard architecture, in view of the fact that it is actually 'modified'.
Another modification provides a path between instruction memory (such as ROM or flash) and the CPU to allow instruction memory words to be treated as read-only data. This technique is used in some microcontrollers, including the Atmel AVR. This allows constant data, such as text strings or function tables, to be accessed without needing to be previously copied into memory data, preserving sparse (and power-hungry) data memory from reading/writing variables. Special machine language instructions are provided to read data from instruction memory. (This is different from the instructions themselves embedding constant data, although for individual constants the two mechanisms can substitute one for the other.)
Speed
In recent years the speed of CPUs has increased a lot compared to the memory it works with, so great attention must be paid to reducing the number of times it is accessed to maintain performance. If, for example, every instruction executed on the CPU requires an access to memory, there is nothing to be gained by increasing the speed of the CPU—this problem is known as memory throttling.
It is possible to make memory much faster, but this is only practical for small amounts of memory for cost, power, and signal routing reasons. The solution, therefore, is to provide a small amount of very fast memory known as the CPU cache. As long as the data needed by the CPU is in the cache, the performance will be much higher than if the cache has to get the data from main memory first.
External vs internal design
Modern high-performance CPU chip designs incorporate aspects of both the Harvard and von Neumann architectures. In particular, the "split cache" of the modified Harvard architecture. The CPU cache is divided into an instruction cache and a data cache. The Harvard architecture is used when the CPU accesses the cache. However, in the case of a cache miss, the data is retrieved from main memory, which is not formally divided into separate instruction and data sections, although it may also have separate memory controllers used for simultaneous access to the memory. RAM, ROM and flash memory (NOR).
Thus, although a von Neumann architecture is visible in some contexts, such as when data and code come from the same memory controller, the hardware implementation gains the efficiencies of the Harvard architecture for cache accesses and in part for some accesses to main memory.
In addition, CPUs often have write buffers that allow it to proceed after writing to uncached regions. Thus, the von Neumann nature of memory becomes apparent when the CPU writes instructions as data and the software must ensure that the caches (data and instructions) and the write buffer are in sync, before attempting to execute those newly written instructions..
Modern Uses of Harvard Architecture
The main advantage of the pure Harvard architecture—simultaneous access to more than one system memory—has been reduced by modified Harvard processors using modern CPU cache systems. Relatively pure Harvard architecture machines are used primarily in applications whose trade-offs, such as the costs and power savings of bypassing the cache, outweigh the programming disadvantages that come with having different code and data address spaces.
- In general, digital signal processors (DSPs) run small highly optimized audio or video processing algorithms. They avoid caches because their behavior must be extremely reproducible. The difficulties of dealing with multiple address spaces are a secondary concern at the speed of execution. Consequently, some DSPs have multiple data memories in different address spaces to facilitate both SIMD and VLIW processing. As an example, the Texas Instruments TMS320 C55x processors have several parallel data buses (two writing, three reading) and an instruction bus.
- Microcontrollers are characterised by having small amounts of program (memory flash) and data memory (SRAM), without cache, and use Harvard architecture to accelerate processing by means of simultaneous access to instructions and data. Separate storage means that memories can differ in bit widths, for example, using 16-bit wide instructions and 8-bit width data. This also means that instructions can be brought before they are needed (prefetching) while other activities are performed in parallel. Examples include the AVR of Atmel Corp and the PIC of Microchip Technology, Inc..
Even in these cases, it is common to use special instructions in order to access program memory as data for the creation of read-only tables or for reprogramming, making them modified Harvard architecture processors.