ARM architecture
ARM, formerly Advanced RISC Machine, originally Acorn RISC Machines, is a RISC architecture (Reduced Instruction Set Computer=Computer with Reduced Instruction Set) of 32 bits and, with the arrival of its version V8-A, also of 64 Bits, developed by ARM Holdings. The ARM architecture is the most widely used 32-bit and 64-bit instruction set in drives produced. Originally conceived by Acorn Computers for use in personal computers, the first ARM-based products were the Acorn Archimedes, released in 1987.
A RISC-based design approach allows ARM processors to require fewer transistors than x86 CISC processors, typical of most personal computers. This design approach leads, therefore, to a reduction in costs, heat and energy. These features are desirable for battery-powered devices such as mobile phones, tablets, etc.
The relative simplicity of ARM processors makes them ideal for low-power applications. As a result, they have become dominant in the mobile and embedded electronics market, embodied in small, low-power, and relatively low-cost microprocessors and microcontrollers. As of 2005, about 98% of the more than 1 billion mobile phones sold used at least one ARM processor. As of 2009, ARM processors are about 90% of all embedded 32-bit RISC processors. It should be mentioned that there is no table of performance equivalences between the different processor technologies that are generally used in consumer electronics, including PDAs, tablets, mobile phones, smart phones, smart watches, portable game consoles, calculators, digital players multimedia (photos, videos, etc.) and computer peripherals such as hard drives and routers.
The ARM architecture is licensable. This means that the main business of ARM Holdings is the sale of IP (intellectual property) cores, these licenses are used to create microcontrollers and CPUs based on this core. Companies that are current or former ARM license holders include Alcatel-Lucent, Apple Inc., AppliedMicro, Atmel, Broadcom, Cirrus Logic, Digital Equipment Corporation, Ember, Energy Micro, Freescale, Intel (through DEC), LG, Marvell Technology Group, Microsemi, Microsoft, NEC, Nintendo, Nokia, Nuvoton, Nvidia, Sony, MediaTek, NXP (formerly Philips Semiconductors), Oki, ON Semiconductor, Psion, Qualcomm, Samsung, Sharp, STMicroelectronics, Symbios Logic, Texas Instruments, VLSI Technology, Yamaha, and ZiiLABS.
ARM processors are developed by ARM and ARM licensees. Prominent families of ARM processors developed by ARM Holdings include the ARM7, V8-A ARM9, ARM11 and Cortex. ARM processors developed by licensee firms include Applied Micro Circuits Corporation X-Gene, DEC StrongARM, Freescale i.MX, Marvell Technology Group XScale, NVIDIA Tegra, Qualcomm Snapdragon, Texas Instruments OMAP, Samsung Exynos, Apple Ax, ST-Ericsson NovaThor, Huawei K3V2 and Intel Medfield.
History
The design of the ARM architecture began in 1983 as a development project by the company Acorn Computers. Sophie Wilson and Steve Furber led the team, whose goal was originally to develop an advanced processor, but with an architecture similar to the MOS 6502. The reason was that Acorn had a long line of personal computers based on that microprocessor, so it made sense to develop one that developers were comfortable with.
The team finished preliminary design and early prototypes of the processor in 1985, which they named the ARM1. The first commercially used version was named ARM2 and was released in 1986.
The ARM2 architecture has a 32-bit data bus and offers a 26-bit address space, along with 16 32-bit registers. One of these registers is used as a program counter, taking advantage of its 4 upper bits and the 2 lower ones to contain the processor status flags.
The ARM2 is probably the world's simplest usable 32-bit processor, having only 30,000 transistors. Its simplicity is due to the fact that it is not based on microcode (a system that usually occupies around a quarter of the total number of transistors used in a processor) and that, as was common at that time, it does not include a cache. Thanks to this, its power consumption is quite low, while offering better performance than a 286. Its successor, the ARM3, includes a small 4 KB cache, which improves repetitive memory accesses.
In the late 1980s, Apple Computer began working with Acorn on new versions of the ARM core. At Acorn they realized that the fact that a processor manufacturer was also a computer manufacturer could turn off customers, so it was decided to create a new company called Advanced RISC Machines, which would be in charge of the design. and management of the new generations of ARM processors. This happened in the year 1990.
This work led to the ARM6, introduced in 1991. Apple used the ARM 610 (based on the ARM6) as the basic processor for its innovative PDA, the Apple Newton. For its part, Acorn used it in 1994 as the main processor in its RiscPC.
The core remained simple despite the changes: in effect, ARM2 has 30,000 transistors, while ARM6 only has 35,000. The idea was for the end user to combine the ARM core with an optional number of integrated peripherals and other elements, being able to create a complete processor tailored to your needs.
The greatest use of ARM technology was achieved with the ARM7TDMI processor, with millions of units in mobile phones and portable video game systems.
DEC licensed the design, which caused some confusion since it already produced the DEC Alpha, and created the StrongARM. Clocked at 233 MHz, this processor consumed only 1 W of power (this power consumption has been reduced in newer versions). This technology later passed into the hands of Intel, as a result of a legal agreement, which integrated it into its line of Intel i960 processors and made competition more arduous.
Freescale (a company spun off from Motorola in 2004), IBM, Infineon Technologies, OKI, Texas Instruments, Nintendo, Philips, VLSI, Atmel, Sharp, Samsung, and STMicroelectronics also licensed the basic ARM design.
The ARM design has become one of the most used in the world, from hard drives to toys. Today, about 75% of 32-bit processors have this chip in their core.
Families
Family | Architecture version | Nucleus | Features | Cache (I/D)/MMU | Actual MIPS @ MHz | Fields of Implementation |
---|---|---|---|---|---|---|
ARM1 | ARMv1 (obsolete) | ARM1 | Null | ARM Evaluation System second processor for BBC Micro | ||
ARM2 | ARMv2 (obsolete) | ARM2 | Added instruction MUL (multiplicate) | Null | 4 MIPS @ 8 MHz 0.33 DMIPS/MHz | Acorn Archimedes, Chessmachine |
ARMv2a (obsolete) | ARM250 | MEMC (MMU), graphics and an E/S processor. Added SWP and SWPB (swap) instructions. | Null, MEMC1a | 7 MIPS @ 12 MHz | Acorn Archimedes | |
ARM3 | ARMv2a (obsolete) | ARM2a | First integration of a cache memory into an ARM. | 4K unified | 12 MIPS @ 25 MHz 0.50 DMIPS/MHz | Acorn Archimedes |
ARM6 | ARMv3 (obsolete) | ARM60 | 32-bit memory steering support (compared to 26-bit) | Null | 10 MIPS @ 12 MHz | 3DO Interactive Multiplayer, Zarlink GPS Receiver |
ARM600 | Like ARM60, cache and cooprocessor bus (for the FPA10) floating comma unit. | 4K unified | 28 MIPS @ 33 MHz | |||
ARM610 | Like ARM60, cache, no coprocessor bus. | 4K unified | 17 MIPS @ 20 MHz 0.65 DMIPS/MHz | Acorn Risc PC 600, Apple Newton Series 100 | ||
ARM7 | ARMv3 (obsolete) | ARM700 | 8 KB unified | 40 MHz | Acorn Risc PC prototype CPU card | |
ARM710 | Like ARM700 | 8 KB unified | 40 MHz | Acorn Risc PC 700 | ||
ARM710a | Like ARM700 | 8 KB unified | 40 MHz 0.68 DMIPS/MHz | Acorn Risc PC 700, Apple eMate 300 | ||
ARM7100 | Like ARM710a, integrated SoC. | 8 KB unified | 18 MHz | Psion Series 5 | ||
ARM7500 | Like ARM710a, integrated SoC. | 4 KB unified | 40 MHz | Acorn A7000 | ||
ARM7500FE | ARM7500, "FE" added a FPA and an EDO memory controller. | 4 KB unified | 56 MHz 0.73 DMIPS/MHz | Acorn A7000+ Network Computer | ||
ARM7TDMI | ARMv4T | ARM7TDMI(-S) | Segmentation of 3 stages, Thumb | null | 15 MIPS @ 16.8 MHz 63 DMIPS @ 70 MHz | Game Boy Advance, Nintendo DS, Apple iPod, Lego NXT, Atmel AT91SAM7, Juice Box, NXP Semiconductors LPC2000 and LH754xx, Actel's CoreMP7 Archived on July 18, 2011 at Wayback Machine. |
ARM710T | ARM7TDMI, cache | 8 KB unified, MMU | 36 MIPS @ 40 MHz | Psion Series 5mx, Psion Revo/Revo Plus/Diamond Mako | ||
ARM720T | ARM7TDMI, cache | 8 KB unified, MMU with FCSE | 60 MIPS @ 59.8 MHz | Zipit Wireless Messenger, NXP Semiconductors LH7952x | ||
ARM740T | ARM7TDMI, cache | MPU | ||||
ARMv5TEJ | ARM7EJ-S | Segmentation of 5 stages, Thumb, Jazelle DBX, improvement of DSP instructions | null | |||
StrongARM | ARMv4 | SA-110 | 16 KB/16 KB, MMU | 203 MHz 1.0 DMIPS/MHz | Apple Newton Series 2x00, Acorn Risc PC, Rebel/Corel Netwinder, Chalice CATS | |
SA-1100 | SA-110, Integrated SoC | 16 KB/8 KB, MMU | 203 MHz | Psion netBook | ||
SA-1110 | SA-110, Integrated SoC | 16 KB/8 KB, MMU | 206 MHz | LART (computer), Intel Assabet, Ipaq H36x0, Balloon2, Zaurus SL-5x00, HP Day 7xx, Day 560 series, Palm Zire 31 | ||
ARM8 | ARMv4 | ARM810 | Segmentation of 5 phases, static leap predilection, double bandwidth memory | 8 KB unified, MMU | 84 MIPS @ 72 MHz 1.16 DMIPS/MHz | Acorn Risc PC prototype CPU card |
ARM9TDMI | ARMv4T | ARM9TDMI | Segmentation of 5 phases, Thumb | null | ||
ARM920T | ARM9TDMI, cache | 16 KB/16 KB, MMU with FCSE (Fast Context Switch Extension) | 200 MIPS @ 180 MHz | Armadillo, Atmel AT91SAM9, GP32, GP2X (first core), Tapwave Zodiac (Motorola i. MX1), Hewlett-Packard HP-49/50 Calculators, Sun SPOT, Cirrus Logic EP9302, EP9307, EP9312, EP9315, Samsung S3C2442 (HTC TyTN, FIC Neo FreeRunner) | ||
ARM922T | ARM9TDMI, caches | 8 KB/8 KB, MMU | NXP Semiconductors LH7A40x | |||
ARM940T | ARM9TDMI, caches | 4 KB/4 KB, MPU | GP2X (second core), Meizu M6 Mini Player | |||
ARM9E | ARMv5TE | ARM946E-S | Thumb, instructions improvement DSP, cache | variables, closely coupled memory, MPU | Nintendo DS, Nokia N-Gage, Canon PowerShot A470, Canon EOS 5D Mark II, Conexant 802.11 chips, Samsung S5L2010 | |
ARM966E-S | Thumb, DSP Instruction Enhancement | No cache, TCMs | ST Micro STR91xF, Ethernet integration | |||
ARM968E-S | ARM966E-S | No cache, TCMs | NXP Semiconductors LPC2900 | |||
ARMv5TEJ | ARM926EJ-S | Thumb, Jazelle DBX, DSP Instruction Enhancement | variables, TCMs, MMU | 220 MIPS @ 200 MHz, | MSM602 Squeezebox Radio; NeoMagic MiMagic Family MM6, MM6+, MM8, MTV; Buffalo TeraStation Live (NAS); Telechips TCC7801, TCC7901;ZiiLABS' ZMS-05 SoC; Western Digital MyBook "I World Edition"; Rockchip RK2806 and RK2808. | |
ARMv5TE | ARM996HS | Watchless processor, like ARM966E-S | without caches, TCMs, MPU | |||
ARM10E | ARMv5TE | ARM1020E | Segmentation of 6 phases, Thumb, Improvement of instructions DSP, (VFP) | 32 KB/32 KB, MMU | ||
ARM1022E | ARM1020E | 16 KB/16 KB, MMU | ||||
ARMv5TEJ | ARM1026EJ-S | Thumb, Jazelle DBX, DSP Instruction Enhancement, (VFP) | variable, MMU or MPU | Western Digital MyBook "II World Edition";Conexant so4610 and so4615 ADSL SoC | ||
XScale | ARMv5TE | 80200/IOP310/IOP315 | E/S Processor, Thumb, DSP Instruction Improvement | |||
80219 | 400/600 MHz | Thecus N2100 | ||||
IOP321 | 600 BogoMips @ 600 MHz | Iyonix | ||||
IOP33x | ||||||
IOP34x | 1–2 cores, RAID accelerator | 32K/32K L1, 512K L2, MMU | ||||
PXA210/PXA250 | Application Processor, 7-phase Segmentation | PXA210: 133 and 200 MHz, PXA250: 200, 300, and 400 MHz | Zaurus SL-5600, iPAQ H3900, Sony CLIÉ NX60, NX70V, NZ90 | |||
PXA255 | 32KB/32KB, MMU | 400 BogoMips @ 400 MHz; 371–533 MIPS @ 400 MHz | Gumstix basix " connex, Palm Tungsten E2, Zaurus SL-C860, Mentor Ranger " Stryder, iRex ILiad | |||
PXA263 | 200, 300 and 400 MHz | Sony CLIÉ NX73V, NX80V | ||||
PXA26x | default 400 MHz, more than 624 MHz | Palm Tungsten T3 | ||||
PXA27x | Application Processor | 32 KB/32 KB, MMU | 800 MIPS @ 624 MHz | PXA270 COM, HTC Universal, HP hx4700, Zaurus SL-C1000, 3000, 3200, Dell Axim x30, x50, and x51 series, Motorola Q, Balloon3, Trolltech Greenphone, Palm TX(312MHz), Motorola Ezēx Platform A728, A7 | ||
PXA800(E)F | ||||||
PXA3XX (name "Monahans") | 32KB/32KB L1, TCM, MMU | 1000 MIPS @ 1.25 GHz | Samsung Omnia | |||
PXA900 | Blackberry 8700, Blackberry Pearl (8100) | |||||
IXC1100 | Flight Control Processor | |||||
IXP2400/IXP2800 | ||||||
IXP2850 | ||||||
IXP2325/IXP2350 | ||||||
IXP42x | NSLU2 IXP460/IXP465 | |||||
ARM11 | ARMv6 | ARM1136J(F)-S | 8-stage segmentation, SIMD, Thumb, Jazelle DBX, (VFP), DSP Instruction Enhancement | variable, MMU | 740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz | Nokia E90, Nokia N93, Nokia N95, Nokia N82, Zune, BUGbase[2], Nokia N800, Nokia N810, Qualcomm MSM7200 |
ARMv6T2 | ARM1156T2(F)-S | Segmentation of 9 stages, SIMD, Thumb-2, (VFP), Improvement of instructions DSP | variable, MPU | |||
ARMv6KZ | ARM1176JZ(F)-S | ARM1136EJ(F)-S | variable, MMU+TrustZone | Apple iPhone (EDGE and 3G), Apple iPod touch (1.a and 2.a generation), Conexant CX2427X, Motorola RIZR Z8, Motorola RIZR Z10, NVIDIA GoForce 6100; Telechips TCC9101, TCC9201, TCC8900, Fujitsu MB86H60, Samsung S3C6410 (e.g. Samsung Omnia II, Samsung Moment, SmartQ 5) | ||
ARMv6K | ARM11 MPCore | As ARM1136EJ(F)-S, 1-4 core SMP | variable, MMU | Nvidia APX 2500, Family Nintendo 3DS | ||
Family | Architecture version | Nucleus | Features | Cache (I/D)/MMU | Actual MIPS @ MHz | Field of application |
Cortex | ARMv7-A | Cortex-A5 | VFP, NEON, Jazelle RCT and DBX, Thumb-2, 8-phase segmentation, 1-4 SMP cores | variable (L1), MMU+TrustZone | More than 1500 (1.5 DMIPS/MHz) | "Sparrow" (keyname) |
Cortex-A8 | VFP, NEON, Jazelle RCT, Thumb-2, 13-stage Superscalar Segmentation | variable (L1+L2), MMU+TrustZone | More than 2000 (2.0 DMIPS/MHz clock from 600 MHz to more than 1 GHz) | Texas OMAP3xx series, SBM7000, Oregon State University OSWALD, Gumstix Overo Earth, Pandora, Apple iPhone 3GS, Apple iPod touch (3rd Generation), Apple iPad (SoCApple A4), Apple iPhone 4 (Soc Apple A4, manufactured by Samsung and Intrensity), Archos 5, FreeScale i.MX51-SOC, BeagleBoard | ||
Qualcomm Scorpion | GPU Adreno 200, VFPv3, NEON, Jazelle RCT, Thumb-2, 13-stage Superscalar Segmentation, | variable (L1+L2), MMU+TrustZone | More than 2000 (2.0 DMIPS/MHz clock from 1 GHz to more than 1.5 GHz dual core) | Toshiba TG01, HTC Desire, Google Nexus One, HTC EVO 4G, HTC Incredible, HTC Scorpion, HTC HD2, HTC HD7 Sony Ericsson Xperia ARC/ARC S | ||
Cortex-A9 | Application profile, (VFP), (NEON), Jazelle RCT and DBX, Thumb-2, Out-of-order speculative issue superscalar | MMU+TrustZone | 2.5 DMIPS/MHz | Acer Iconia A200, Galaxy Nexus, Motorola RAZR | ||
Cortex-A9 MPCore | Cortex-A9, 1–4 SMP cores | MMU+TrustZone | 10,000 DMIPS @ 2 GHz optimized on TSMC 40G (Dable Core) (2.5 DMIPS/MHz per kernel) | Texas Instruments OMAP4430/4440, ST-Ericsson U8500, Nvidia Tegra2, Qualcomm Snapdragon 8X72 PlayStation Vita, Samsung Galaxy S II (Exynos 4210), Samsung Galaxy S III (Exynos 4212) | ||
ARMv7-R | Cortex-R4(F) | Embedded Profile, Thumb-2, (PU) | cache variable, optional MPU | 600 DMIPS @ 475 MHz | Broadcom, TMS570 from Texas Instruments | |
ARMv7-ME | Cortex-M4 (name "Merlin") | Microcontroller profile, Thumb and Thumb-2, UF. MAC, SIMD and split instructions. | Optional MPU. | 1.25 DMIPS/MHz | ||
ARMv7-M | Cortex-M3 | Microcontroller profile, Thumb-2 only. Handle of instructions by Hardware. | No cache, optional MPU. | 125 DMIPS @ 100 MHz | Texas Instruments Stellaris microcontroller family, ST Microelectronics STM32, NXP Semiconductors LPC1700, Toshiba TMPM330FDFG Archived on 14 June 2011 at Wayback Machine., Ember's EM3x Series, Atmel AT91SAM3, Europe Technologies EasyBCU, Energy Micro's EFM32, Actel's SmartFusion Archived on 18 June | |
ARMv6-M | Cortex-M0 (name "Swift") | Microcontroller profile, Thumb-2 subset (instructions 16-bit Thumb & BL, MRS, MSR, ISB, DSB, and DMB). | No cache. | 0.9 DMIPS/MHz | NXP Semiconductors NXP LPC1100, Triad Semiconductor, Melfas, Chungbuk Technopark, Nuvoton, austriamicrosystems, Rohm | |
Cortex-M1 | FPGA targeted, Microcontroller profile, Thumb-2 subset (instructions 16-bit Thumb & BL, MRS, MSR, ISB, DSB, and DMB). | No | More than 136 DMIPS @ 170 MHz (0.8 DMIPS/MHz, MHz achievable FPGA-dependent) | Actel ProASIC3, ProASIC3L, IGLOO and Fusion PSC devices Archived on July 7, 2011 at Wayback Machine., Altera Cyclone III, other FPGA products are supported, for example: Synplicity | ||
Family | Architecture version | Nucleus | Features | Cache (I/D)/MMU | Actual MIPS @ MHz | Field of Application |
Design
The ARM instruction set is similar to that of the MOS 6502, but includes additional features that allow it to achieve better execution performance. To maintain the traditional concept of RISC, the execution of an order was established in a time, generally, one cycle. The most interesting feature is the use of the upper 4 bits as a condition code, making any instruction conditional. This cut reduces the space for some memory access offsets, but allows you to avoid wasting clock cycles in the pipeline when executing small pieces of code with conditional execution. The typical example is the Greatest Common Divisor, according to Euclid's algorithm.
C example:
while (i = j) // Enter in the cycle when i tendj or i rigidj, not when i=j { if (i ▪ j) // When i rigidj performs the following i -= j; else // in another case, perform the following j -= i; !
In contrast with ARM assembly code, the loop can be made more efficient by doing:
loop: // Comparison i and j GT = i ▪ j; LT = i . j; NE = i = j; // Improved operations using flag results if(GT) i -= j; // Sustrae * only if it's older if(LT) j -= i; // Sustrae * only if it is minor if(NE) drip loop; // Cycle *only* if comparative values are not equal
and this is coded as:
loop: CMP Ri, Rj establishes the condition "NE" if (i != j), ; "GT" if (i /2005 j), ; or "LT" if (i ≥ j) SUBGT Ri, Ri, Rj ; if "GT" (Maybe), i = i-j; SUBLT Rj, Rj, Ri ; if "LT" (Lord than), j = j-i; BNE loop ; if "NE" (Not equal), then perform the cycle
Another unique feature of the instruction set is the ability to add shifts and rotate in data processing (arithmetic, logical, and register movement), for example, the C instruction "a += (j <<2);" it can be enhanced as a single instruction on the ARM, allowing register relocation.
All of this means that fewer load and save operations are needed, improving performance.
The ARM processor also has some features that are rare in other architectures also considered RISC, such as relative addressing, and pre and post increment addressing mode.
It has two operating modes: ARMI with instructions that occupy 4 bytes, faster and more powerful (there are instructions that are only in this mode) but with greater memory and electricity consumption. And the THUMB mode, more limited, with instructions that occupy 2 bytes and with lower current consumption.
Logs
The ARM family has 16 registers (usable by the programmer) of 32 bits each, designated from R0 to R15. In principle, they are all identical and only 3 have specific functions, which are R15 (used as a program or PC counter), and R14 (used to store the return address when a subroutine is called or an exception is generated) and the R13 (stack pointer).
Advantages
- Wide range of manufacturers: As discussed above, ARM allows third-party purchase of your license, giving rise to a large number of manufacturer brands of this architecture, each offering new improvements, advances, and, in general, a wider range of consumer options.
- Simple instructions: We find a much smaller set of instructions, but much more atomic; this means that the instructions can be changed practically by machine type instructions, saving both time and energy in their translation.
- Low energy use: We meet RISC, and its "simpleness". They seek the greatest efficiency per cycle; they also result in smaller and simple chips and, therefore, a considerable improvement in energy efficiency.
- Acceptable performance and improvement: As mentioned above, the purchase of third parties offers new improvements and progress in performance.
Technologies
Thumb
Newer processors come with an additional instruction set called Thumb, which is 16 bits (2 bytes) long per instruction, instead of 32 bits (4 bytes) as the standard ARM set.. Thumb is a subset of the most frequently used instructions. By having half the length, it is possible to reduce the amount of code and improve its density. Performance may be better than 32-bit code where the memory port or communications bus width is less than 32-bit. Typically, a small range of memory addresses are inserted into applications with a 32-bit datapath (for example: Game Boy Advance), and the rest are 16 bits in wide mode. or narrower.
The first processor with Thumb technology was the ARM7TDMI. All of the post-ARM9 family, including the Intel XScale processor, have the technology built into their core.
Jazelle
ARM has implemented technology that allows certain types of architectures to run Java bytecode natively on hardware. The first processor to use Jazelle was the ARM926EJ-S, all processors that support this technology being named with a J.
Operating systems
Acorn systems
The first ARM-based personal computer is the Acorn Archimedes that ran an interim operating system called Arthur, which became RISC OS, used on later models from Acorn and other vendors.
Embedded operating systems
The ARM architecture is supported by a large number of embedded and real-time operating systems, including Android, Windows CE, Windows 8 RT,.NET Micro Framework, Symbian, ChibiOS/RT, FreeRTOS, eCos, Integrity, Nucleus PLUS, MicroC/OS-II, QNX, RTEMS, BRTOS, RTXC Quadros, ThreadX, Unison Operating System, uTasker, VxWorks, MQX and OSE.
UNIX
The systems that accredit the standard UNIX specification and that support the ARM architecture are:
- Solaris
UNIX type
Supported UNIX variants are:
- BSD
- Linux
- Plan 9 from Bell Labs
- Apple iOS
Linux
The following Linux distributions support ARM processors:
- Ubuntu
- Arch Linux
- Kali Linux
- Manjaro
- Gento Linux
BSD
The following BSD systems support ARM processors:
- FreeBSD
- NetBSD
- OpenBSD
- RISC iX (only systems based on Acorn ARM2/ARM3)
Windows
Microsoft announced on January 5, 2011 that the next major version of the Windows NT family (now Windows 8) includes support for ARM processors. Microsoft showed a preview version of Windows (version 6.2.7867) running on an ARM-based computer at the 2011 Consumer Electronics Show. The ARM architecture is also supported by Microsoft's mobile operating systems, Windows Phone and Windows Mobile. ARM also supports Windows Embedded CE which is now called Windows Embedded Compact. This latest version supports ARM 5,6 and 7. Windows CE 5 is the underlying operating system for Windows Mobile and Windows Embedded Compact 7 is the underlying operating system for Windows Phone 7. The small Microsoft OS.NET Microframework exclusively uses ARM.
On October 29, 2012, the Microsoft Surface tablet went on sale, which has an ARM processor and uses Windows 8 RT as the operating system, a version that cannot be downloaded or purchased since it is installed on tablets with ARM architecture. There is another version of Windows 8 other than this which is Windows 8 PRO for x86 computers.
Recently we have been working on a Windows 10 x86 architecture emulator for ARM processors on a specific processor brand.
IOS and macOS
Since the development of the iPhone in 2007, Apple has used ARM processors for its mobile phone platforms (iPhone), smartwatches (Apple Watch), tablets (iPad), and most recently in laptop computers (Mac Books). Apple chose ARM processors for these platforms because of the advantage they offer in low power consumption and little cooling required.
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