AMD Opterons

format_list_bulleted Contenido keyboard_arrow_down

ImprimirCitar

Opteron is a line of AMD x86 microprocessors for servers and workstations, and was the first x86 architecture microprocessor to use the AMD64 instruction set, also known as x86-64. It was released on April 22, 2003 with the SledgeHammer (K8) core and was intended to compete in the server and workstation market, particularly in the Intel Xeon processor segment. Processors based on the AMD K10 architecture (Barcelona) were announced on September 10, 2007, incorporating a new quad-core configuration. The most recent release of Opteron processors is the Opteron 4300 and 6300 series processors ("Seoul" and "Abu Dhabi" respectively) based on the Piledriver architecture.

Technical description

Two key capabilities

Opteron combines two important capabilities in a single processor:

Native execution of x86 32-bit applications without loss of performance
Native application execution x86-64 64-bit

The first feature is notable because at the time of the Opteron's introduction, the only 64-bit architecture available on the market with x86 32-bit compatibility (Intel's Itanium) ran native x86 applications only with a significant loss of performance. speed. The second capability, by itself, is less important, since older RISC architectures (such as SPARC, Alpha, PA-RISC, PowerPC, MIPS) have been 64-bit for many years. With the combination of these two capabilities, however, the Opteron gained recognition for its ability to economically run the large installed base of x86 applications, while also offering a path to upgrade systems to 64-bit.

Opteron processors have an integrated memory controller supporting DDR SDRAM, DDR2 SDRAM or DDR3 SDRAM (depending on processor generation). This eliminates the latency to access the main RAM and eliminates the need for a separate IC for the north bridge.

Multithreading Features

Opteron "Barcelona" of four cores.

They chose "Istanbul" of six cores.

In multithreaded systems (more than one Opteron on a single motherboard), CPUs communicate using Direct Connect Architecture over high-speed HyperTransport links. Each CPU can access the main memory of the other processor, this being transparent to the programmer. The way the Opteron performs multiprocessing is not the same as symmetric multiprocessing; instead of having one memory bank for all CPUs, each CPU has its own memory. Therefore, the Opteron is of Non-Uniform Memory Access (NUMA) architecture. The Opteron CPU supports up to an 8-way configuration in mid-tier servers. In enterprise level servers additional (and expensive) router ICs are used to support more than 8 CPUs per box.

In various benchmarks, the Opteron has been shown to have better multiprocessing scalability than the Intel Xeon. This is mainly because adding an additional Opteron processor increases memory bandwidth, which is not always This is the case with Xeon-based systems, and the fact that Opterons use switches instead of a shared bus. In particular, the Opteron's integrated memory controller allows the CPU to access local RAM quickly. In contrast, Xeon CPUs in a multiprocessor system share only two buses for processor-processor and processor-memory communications. When the number of CPUs in a typical Xeon system increases, the contention of the shared buses causes a drop in system efficiency. Intel is migrating to an Opteron-like memory architecture for the Intel Core i7 family and its Xeon derivatives.

Multicored Opterons

AMD introduced its first multicore Opterons in April 2005. At the time, AMD used the term multicore as a synonym for dual core; each physical Opteron contains two processing cores. This effectively doubles the processing power available in each processor socket on the motherboard. Each socket can deliver the performance of two processors, two sockets can deliver the performance of four processors, and so on. Because the cost of the motherboard increases dramatically as CPU sockets are added, multicore processors allow you to build multiprocessor systems at low cost.

AMD's model number scheme has changed a bit with the new multicore lineup. When they were introduced, AMD's fastest multicore Opteron was the 875 model, with two cores running at 2.2 GHz each. The fastest single-core Opteron was the 252 model, running at 2.6 GHz. For multi-threaded applications, or several single-threaded applications, the 875 model could run much faster than the 252 model.

Second-generation Opterons are offered in three series: the 1000-series (single-socket, meaning only one processor on the motherboard), the 2000-series (for two-socket, two processors on the motherboard), and the 8000 series (four or eight sockets). The 1000 series use the AM3 socket. The 2000 and 8000 series use socket F.

AMD announced its third-generation quad-core processors in September 2007, hardware vendors announcing their servers the following month. Based on the core design called Barcelona, new power and temperature control techniques were planned for the chips. The first dual-core DDR2-based platforms were upgradeable to quad-core microprocessors. The fourth generation was announced in June 2009 with the Istanbul six-core. The HT Assist was introduced, an additional directory for the location of the data, which reduces consumption for polling and emissions. HT Assist uses 1 MB L3 cache per CPU when activated.

In March 2010 AMD released the Opteron 6100 Magny-Cours series of CPUs for the G34 socket. These CPUs for 8 and 12 core multichip modules consist of two 4 or 8 core dies with a HyperTransport 3.1 link linking the two. These CPUs upgraded multi-socket Opteron platforms to use DDR3 memory and increased the maximum HyperTransport link speed from 2.4 GHz (4.8 GT/sec), for Istanbul CPUs, to 3, 2GHz (6.4 GT/sec)

AMD changed the naming scheme for its Opteron models. The Opteron 4000 series in socket C32 (released in July 2010) supports dual socket and is geared towards single-processor and bi-processor systems. The Opteron 6000 series in socket G34 supports quad socket and is oriented to high-end bi-processor and tetra-processor systems.

Socket 939

AMD released the Opteron for socket 939, lowering the cost of low-end server and workstation motherboards. Except for the fact that they have 1 MB L2 cache (versus the Athlon64's 512 KB), the Opteron for socket 939 is identical to the Athlon 64 with San Diego and Toledo cores, but they run at speeds lower than they support, being of this way more stable.

Socket AM2

Socket AM2 Opterons are available for servers but only in single-processor configuration. The dual-core Opterons named Santa Ana, rev. F, they have a 2x1 MB L2 cache, unlike most of their Athlon 64 X2 cousins, which have a 2x512 KB L2 cache. These CPUs have model numbers from 1210 to 1224.

Socket AM2+

AMD introduced the quad-core Opterons for socket AM2+ for uniprocessor servers in 2007. These CPUs are built on the 65nm process and are similar to the Phenom X4 Agena. Quad core Opterons for AM2+ are called "Budapest". These Opterons carry the model numbers 1352 (2.1 GHz), 1354 (2.2 GHz), and 1356 (2.3 GHz.)

Socket AM3

AMD introduced the quad-core Opterons for socket AM3 for uniprocessor servers in 2009. These CPUs are built on the 45nm process and are similar to the Phenom II X4 Deneb. Quad-core Opterons for socket AM3 are called "Suzuka." These Opterons carry the model numbers 1381 (2.5 GHz), 1385 (2.7 GHz), and 1389 (2.9 GHz.)

Socket F

Socket F (LGA 1207 pin) is the second generation socket for AMD Opterons. This socket supports Santa Rosa, Barcelona, Shanghai and Istanbul processors. The “Lidded land grid array” socket adds support for DDR2 SDRAM memory HyperTransport version 3 enhanced connectivity. The socket and microprocessor package are physically identical to, but not compatible with, the 1207 FX socket.

Socket G34

Socket G34 (LGA 1944 pin) is one of Opteron's third generation sockets, along with socket C32. This socket supports the Bulldozer-based Opteron 6100 Magny-Cours, Opteron 6200 Interlagos, and Opteron 6300 "Abu Dhabi" based on Piledriver. This socket supports four channels of DDR3 SDRAM memory (two per CPU die). Unlike multi-processor Opteron sockets, socket G34 CPUs work with unbuffered ECC or non-ECC RAM, in addition to traditional ECC RAM.

Socket C32

The C32 socket (LGA 1207 pin) is the other member of the third generation Opteron sockets. This socket is similar to socket F but is not compatible with it. Socket C32 uses DDR3 SDRAM and is different to prevent inserting a socket F CPU that uses only DDR2 memory. Like the G34, the C32 socket works with unbuffered ECC or non-ECC RAM, in addition to traditional ECC RAM.

Micro-architecture update

The Opteron line saw an update with the implementation of the AMD K10 micro-architecture. The new processors, launched in the third quarter of 2007 (called Barcelona), incorporated several improvements, particularly in memory data prefetching, speculative loading, SIMD execution and branch prediction, giving as The result is a measurable improvement over the K8-based Opterons, with the same current draw.

Meanwhile, AMD has also used a new scheme to characterize the power consumption of new processors based on "average" daily consumption, called average CPU power (ACP). the CPU).

FT3 Socket

Opteron X1150 and Opteron X2150 APUs are used with BGA-769 or Socket FT3.

Models

Opterons for Socket 940 and Socket 939 have a three-digit model number, in the form Opteron XYY. For Socket F and Socket AM2 Opterons, each processor has a four-digit model number, in the form Opteron XZYY. For the first, second, and third generation Opterons, the first digit (the X) specifies the number of CPUs on the machine for which it is intended:

1 - designed for systems with a processor.
2 - designed for systems with two processors.
8 - designed for systems with four or eight processors.

On Socket F and Socket AM2 Opterons, the second digit (the Z) represents the generation of the processor. Currently, only 2 (dual core, DDR2), 3 (quad core, DDR2) and 4 (six core, DDR2) are used.

Socket C32 and G34 Opterons use a four-digit numbering scheme. The first digit refers to the number of CPUs on the machine for which it is intended.

4 - Designed for systems with one and two processors.
6 - Designed for systems with two and four processors.

As with the second and third generation Opterons, the second number indicates the generation of the processor. "1" refers to drives based on AMD K10 (Magny-Cours and Lisbon), "2" refers to Interlagos, Valencia and Zurich Bulldozer units, and "3" refers to units based in Piledriver Abu Dhabi, Seoul and Delhi.

For all Opterons, the last two digits in the model number (the YY) indicate the CPU clock frequency, a higher number indicates a higher clock frequency. This speed is comparable to processors of the same generation if they have the same number of cores; single-core and dual-core are indicated differently even though they have the same clock frequency.

The suffix HE or EE indicates that it is a model of high efficiency and low consumption (Hhigh-Efficiency, Energy-Efficiency) having a lower TDP than the Opteron standard. The SE suffix indicates a top-of-the-line model with a higher TDP than the standard Opteron.

Starting with the 65nm manufacturing process, the Opteron's code names are based on the cities that hosted Formula 1 races. AMD has long been a sponsor of Formula One's most successful team 1, Ferrari.

AMD Opteron Family Processors
Name	Process	Date	Nucles
SledgeHammer Venus Troy Athens	130 nm 90 nm 90 nm 90 nm	June 2003 August 2005 January 2006 January 2006	1
Denmark Italy Egypt Santa Ana Santa Rosa	90 nm 90 nm 90 nm 90 nm 90 nm	March 2006 May 2006 June 2006 August 2006 August 2006	2
Barcelona Budapest Shanghai	65 nm 65 nm 45 nm	September 2007 April 2008 November 2008	4
Istanbul	45 nm	January 2009	6
Lisbon	45 nm	January 2010	4.6
Magny-Cours	45 nm	March 2010	8.12
Valencia	32 nm	November 2011	6.8
Interlagos	32 nm	November 2011	4,8,12,16
Zurich	32 nm	March 2012	4, 8
Abu Dhabi	32 nm	November 2012	4,8,12,16
Delhi	32 nm	December 2012	4, 8
Seoul	32 nm	December 2012	4, 6, 8
Annex:AMD Opteron Processors

Opteron (130nm SOI)

A core – SledgeHammer (1yy, 2yy, 8yy)

CPU-Steppings: B3, C0, CG
Cache L1: 64 + 64 KB (Data + Instructions)
L2 Cache: 1024 KB, maximum speed
MMX, Extended 3DNow!, SSE, SSE2, AMD64
Socket 940, 800 MHz HyperTransport
DDR SDRAM registered required for socket 940, possible ECC
VCore: 1.5 V - 1.55 V
Maximum consumption (TDP): 89 W
First Release: 22 April 2003 [1]
Multiplication of clock 1,4–2,4 GHz (x40 - x50)

Opteron (90nm SOI, DDR)

A core – Venus (1yy), Troy (2yy), Athens (8yy)

CPU-Steppings: E4
Cache L1: 64 + 64 KB (Data + Instructions)
L2 Cache: 1024 KB, maximum speed
MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64
Socket 940, 800 MHz HyperTransport
Socket 939/Socket 940, 1000 MHz HyperTransport
DDR SDRAM registered required for socket 940, possible ECC
VCore: 1.35 V - 1.4 V
Maximum consumption (TDP): 95 W
Bit NX
Check 64-bit segment limit for VMware style virtualization with binary translation.
Optimized Power Management (OPM)
First Release: 14 February 2005
Watch Multiplication: 1.6 - 3.0 GHz (x42 - x56)

Double core – Denmark (1yy), Italy (2yy), Egypt (8yy)

CPU-Steppings: E1, E6
First Release: Spring 2005
Watch multiplication: 1.6–2,8 GHz (x60, x65, x70, x75, x80, x85, x90)
...
Socket 939/Socket 940, 1000 MHz HyperTransport
...
Bit NX

Opteron (90nm SOI, DDR2)

Double core – Santa Ana (12yy), Santa Rosa (22yy, 82yy)

CPU-Steppings: F2, F3
Cache L1: 64 + 64 KB (Data + Instructions)
L2 Cache: 2*1024 KB, maximum speed
MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64
Socket F, 1000 MHz HyperTransport - Opteron 2yy, 8yy
Socket AM2, 1000 MHz HyperTransport - Opteron 1yy
VCore: 1.35 V
Maximum consumption (TDP): 95 W
Bit NX
Virtualization AMD-V
Optimized Power Management (OPM)
First release: 2006
Watch Multiplication: 1.8–3.2 GHz (x10, xx12, xx14, xx16, xx18, xx20, xx22, xx24)

Opteron (65nm SOI)

4 cores – Barcelona (23xx, 83xx) 2360/8360 and lower, Budapest (13yy) 1356 and lower

CPU-Steppings: BA, B3
Cache L1: 64 + 64 KB (Data + Instructions) per core
L2 Cache: 512 KB, maximum speed per core
Cache L3: 2048 KB, shared
MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, SSE4a
Socket F, Socket AM2+, HyperTransport 3.0 (1.6 GHz-2 GHz)
DDR2 registered SDRAM required, possible ECC
VCore: 1.2 V
Maximum consumption (TDP): 95 Watts
Bit NX
Second-generation AMD-V virtualization with Rapid Virtualization Indexing (RVI)
Split power dynamic power management
First Release: September 10, 2007
Watch Multiplication: 1.7–2,5 GHz

Opteron (45nm SOI)

4 cores – Shanghai (23xx, 83xx) 2370/8370 and lower, Suzuka (13yy) 1381 and lower

CPU-Steppings: C2
Cache L3: 6 MB, shared
Watch Multiplication: 2,3–2,9 GHz
HyperTransport 1.0, 3.0
Reduction of 20% of consumption with the unemployed processor [2]
Memory support DDR2 800 MHz (Socket F)[3]
Memory support DDR3 1333 MHz (Socket AM3)

6 cores – Istanbul (24xx, 84xx)

Sold on January 1, 2009.

CPU-Steppings: D0
Cache L3: 6 MB, shared
Watch Multiplication: 2,2–2,8 GHz
HyperTransport 3.0
HT Assist
Memory support DDR2 800 MHz [4]

eight cores – Magny-Cours MCM (6124-6140)

Released March 29, 2010.

CPU-Steppings: D1
Multi-chip module, consisting of two four-core CI
Cache L2: 8x512 KB
Cache L3: 2x6 MB, shared
Watch Multiplication: 2.0–2.6 GHz
Four HyperTransport from 3.1 to 3.2 GHz (6.4 GT/sec)
HT Assist
Memory support DDR3 1333 MHz
Socket G34

12 cores – Magny-Cours MCM (6164-6180SE)

Marketed on March 29, 2010

CPU-Steppings: D1
Multi-chip module, consisting of two six-core CI
Cache L2: 12x512 KB
Cache L3: 2x6 MB, shared
Watch Multiplication: 1.7–2,5 GHz
Four HyperTransport from 3.1 to 3.2 GHz (6.4 GT/sec)
HT Assist
Memory support DDR3 1333 MHz
Socket G34

4 cores – Lisbon (4122, 4130)

Sold on June 23, 2010

CPU-Steppings: D0
Cache L3: 6 MB
Watch Multiplication: 2.2 GHz (4122), 2.6 GHz (4130)
Two HyperTransport links to 3.2 GHz (6.40 GT/sec)
HT Assist
Memory support DDR3 1333 MHz
Socket C32

6 cores – Lisbon (4162-4184)

Sold on June 23, 2010

CPU-Steppings: D1
Cache L3: 6 MB
Watch Multiplication: 1.7-2.8 GHz
Two HyperTransport links to 3.2 GHz (6.40 GT/sec)
HT Assist
Memory support DDR3 1333 MHz
Socket C32

Opteron (32 nm SOI) - Bulldozer Microarchitecture

4 cores - Zurich (3250-3260)

Released on March 20, 2012.

CPU-Steppings: B2
One CI with one Bulldozer processor
Cache L2: 2x2 MB
Cache L3: 4 MB
Watch Multiplication: 2.5 GHz (3250) - 2.7 GHz (3260)
HyperTransport 3 (5.2 GT/sec)
HT Assist
Memory support DDR3 1333 MHz
Turbo CORE support up to 3.5Ghz (3250), up to 3.7Ghz (3260)
Supports single processor configurations only
Socket AM3+

8 cores - Zurich (3280)

Released on March 20, 2012.

CPU-Steppings: B2
One CI with one Bulldozer processor
Cache L2: 4x2 MB
Cache L3: 8 MB
Watch Multiplication: 2.4 GHz
HyperTransport 3 (5.2 GT/sec)
HT Assist
Memory support DDR3 1866 MHz
Support for Turbo CORE, up to 3.5Ghz
Supports single processor configurations only
Socket AM3+

6 cores - Valencia (4226-4238)